Typically in the electronic component world, integrated circuits (IC's) are fabricated on a semiconductor substrate, known as a chip, and most commonly are made of silicon. The silicon chip is typically assembled into a larger package which serves to provide effective enlargement of the distance or pitch between input/output contacts of the silicon making it suitable for attachment to a printed circuit board, and to protect the IC from mechanical and environmental damage. With the trend moving to more and more features packed into decreasing product envelopes, utilizing ever smaller electronic components to improve upon size and feature densification a constant and formidable challenge is presented to manufacturers of consumer and related articles.
Recently the semiconductor industry has introduced reduced package sizes, such as those in area array format Vs more typical peripheral attach of the input and output (I/O) terminals as in lead frame construction. However, the area on the printed circuit board (PCB) occupied by the package is still much larger than the area occupied by the silicon chip. The challenge to reduce size and increase density has been felt by the printed circuit board industry, and has resulted in finer lines and closer pad spacing for IC device contacts.
Not only is area of the device of concern, but also the height or thickness, and the overall weight. These issues have been of particular concern to the variety of portable electronic products in use and under development. Integrated circuit chips, as well as the assembled packages have become thinner. There were early concerns that thinning brittle silicon wafers onto which a plurality of chips have been fabricated would lead to an increase in breakage and yield loss. However, these fears were rapidly dispelled as it was realized that thinner wafers were somewhat compliant and were capable of being flexed without breakage. Methods to backlap or grind away the semiconductor substrate were developed for a number of applications. (*) U.S. Pat. No. 5,160,560.
Many companies have been trying to solve the problem of excessive semiconductor package size, and associated performance loss by directly attaching the chip (DCA) to the board without use of a traditional package. However, they have met with varying degrees of success, and with numerous technical challenges not yet overcome.
Direct chip attach has been most commonly via solder bumps or balls from the input/output (I/O) contacts of the chip interconnecting to the PC Board, and providing both electrical and mechanical connections. Because the materials of the silicon chip and the PC board have different rates of thermal expansion, severe stresses are introduced to the solder connection between the rigid chip and the more thermally expansive board. The stresses caused by the thermal expansion coefficient (CTE) mismatch occur during solder reflow, and as power to the IC is cycled on and off. The stresses typically cause mechanical failure in one or more solder joints, and in turn result in electrical failure of the product.
Chip scale packages (CSP) were developed to provide an alternative solution to directly attached flip chips devices. These packages (CSP) represent a new miniature type of semiconductor packaging used to address the issues of size, weight, and performance in electronic products, especially those for consumer products such as telephones, pagers, portable computers, video cameras, etc. Standards have not yet been formalized for CSP, and as a result, many variations exist, and several of which are described in “Chip Scale Package”, cited above. In general, the chip is the dominant constituent of a CSP with the area of the package, being no more than 20% greater than the area of the chip itself, but the package has supporting features which make it more robust than direct attachment of a flip chip.
Unfortunately, many chip scale packages suffer similar solder fatigue failures as the DCA flip chip devices. To alleviate the problem, and distribute the stresses, a polymeric filler or under-encapsulant is introduced in liquid form by capillary action to surround the solder balls and fill the void between the chip or CSP and a PC board. The “underfill” cures to a rigid form via time, temperature, ultraviolet exposure, or some combination of theseof.
The “underfill” process has a number of drawbacks, including but not limited to the following: a tedious and time consuming process which must be accomplished by the IC customer, voids being entrapped under the device which lead to stress related failures, poor adhesion of the underfill to one or more of the components resulting in localized stresses, difficult if not impossible to rework process, and fillets of “underfill” material around the perimeter of the device which consume additional board space.
Accordingly, a need exists in the industry for a reliable, true chip scale package which eliminates the need for underfill.